1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor. More particularly, the present invention relates to a method for manufacturing an embedded memory with different spacer widths.
2. Description of Related Art
In order to decrease the semiconductor manufacturing cost and simplify the fabrication procedures, a method for putting memory and logic devices together on a semiconductor chip is developed.
Typically, an embedded DRAM comprises a memory device region and a logic circuit region. The memory devices and the logic devices are together formed on the same wafer. The benefits of the embedded DRAM include high yield, short cycle time and low manufacturing cost. However, the specific requirements of the memory devices and the logic devices are different from each other, so that the procedures for manufacturing the embedded DRAM must be modified to fit those requirements. Taking the logic device as an example, the logic device requires a relatively high operation rate. Therefore, it is necessary to form a silicide layer on the surface of the source/drain region in the logic device. However, the formation of the silicide layer on the surface of the source/drain region in the memory device leads to a leakage issue for the capacitor. Hence, before forming a silicide layer on the surface of the source/drain region, it is necessary to additionally form a protective layer such as a silicon nitride layer over the memory device region in the embedded DRAM. The protective layer is then removed after the silicide layer is formed.
Additionally, with the increase in the integration, the line width and the space between the gate structures are decreased. The spacer width of the spacer formed on the sidewall of the gate structure must be decreased to provide enough space for forming a bit line contact or a storage node contact. However, the space width of the logic device is not decreased when decreasing the size of the embedded DRAM because the logic device with a high performance must fit the requirement of high operation rate and large process window. Therefore, it is difficult to simultaneously form a memory device and a logic device in an embedded DRAM.